Standard system buses, such as ISA (Industry Standard Architecture) and EISA (Extended ISA) buses, are conventionally used in personal computers. Another standard bus, PCI (Peripheral Component Interconnect) bus, is commonly employed in desktop-type personal computers to increase the speed of data transfer and organize system architecture, independently of the kind of processors.
In a PCI bus, block transfer is the basis of substantially all data transfer. Transfer of each block is executed by burst transmission. For example, a maximum data transfer speed of 133 megabytes/sec. can be used on a data bus having a width of 32 bits.
Therefore, when a PCI bus is used, data transfer between I/O devices and between a system memory and an I/O device is executed at high speed. As such, system performance is increased.
Recently, PCI busses are used not only in desktop type personal computers, but also in portable personal computers, such as notebook-type computers.
In this type of PCI bus system architecture, a bridge LSI for connecting a PCI bus and an ISA bus is provided, and it bi-directionally converts bus cycles between the PCI bus and the ISA bus.
There are no problems where the bridge LSI operates as a bridge for converting bus cycles from the PCI bus to the ISA bus, but where it operates as a bridge for converting bus cycles from the ISA bus to the PCI bus (i.e. where an ISA I/O device operates as a bus master to access a device on the PCI bus), there is the danger that access by the ISA bus master cannot be correctly executed due to a target retry which is one characteristic of PCI bus system architecture.
Target retry is an inherent PCI device function in PCI bus systems, and is performed in the following manner.
In a PCI bus system, where a target address-specified by a transaction on a PCI bus cannot correspond to the transaction, notification is given of a retry and transaction conclusion to an initiator which commenced the transaction, i.e. a PCI bus master. This type of target retry occurs when a device specified as the target is locked due to exclusive access by another PCI bus master, when exclusively used under OS management. The PCI bus master notified of the retry must release the PCI bus. The operation of a PCI bus master to which a target retry is notified is illustrated in FIG. 1.
A PCI bus master outputs a bus access request signal REQ# to a PCI bus arbiter to request bus access. The PCI bus master waits until having been granted a signal GNT# indicating bus access enable from the PCI bus arbiter. Upon receiving a GNT#, the PCI bus master activates a frame signal FRAME# and commences a transaction.
At this time, where a target specified by the address outputted from the PCI bus master cannot respond to the transaction, a target activates a target ready signal TRDY#, a stop signal STOP# and a device select signal DEVSEL# on the PCI bus as "H", "L" and "L" as shown in FIG. 1, whereby the PCI bus master is notified of a target retry.
The PCI bus master makes the REQ# inactive, invalidates the GNT# and temporarily releases the PCI bus. Thereby, another bus master can use the PCI bus. When a fixed time period has lapsed after notification of the target retry, the PCI bus master retries the same transaction again. If a target retry is not generated in this transaction, the data transfer between the PCI bus master and the target is executed correctly. All of the necessary data transfer has been completed, the PCI bus master makes the REQ# inactive and releases the PCI bus.
However, there is no concept of target retry in the ISA bus system. In the ISA bus system, if the ISA bus cycle must finish midway, the same cycle does not occur again.
Hence, when an ISA bus master has commenced a bus cycle for accessing a device on the PCI bus, and once the above described target retry has been generated, the ISA bus master cannot correctly execute the necessary data write/read.